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6290 sequence drive, san diego, california 92121-4358 800-755-2622 fax: 619-450-9885 http://www.amcc.com S5920 32-bit pci bus target interface february 12, 1997 revised october 1998 f e a t u r e s ? pci 2.2 compliant target/slave device ? full 132 mbytes/sec transfer rate ? pci bus operation dc to 33 mhz ? add-on bus 8 mhz to 40 mhz ? programmable prefetch and wait states ? 8/16/32 bit add-on user bus ? four definable pass-thru regions ? 32 byte burstable pci bus fifo ? active/passive add-on bus operation ? mail box registers w/byte level status ? direct mail box data strobe/interrupt pin ? mail box read/write interrupts ? direct pci & add-on interrupt pins ? s5933 pci target mode replacement ? s5933 software compatible ? plug-n-play compatible ? two wire serial bus nvram support ? optional external bios ? 160 pin pqfp a p p l i c a t i o n s ? isa to pci local bus conversions ? i/o communications ports ? high speed data output ? general purpose pci interfacing ? data communications ? memory interfaces ? data acquisition ? data encryption/decryption d e s c r i p t i o n the amcc S5920 was developed to provide the designer with a single multi-function device offering a flexible and easy means to connect applications to the pci local bus. designers connecting to the pci local bus through the S5920 eliminate the necessity to understand complex pci bus timing requirements and the time consuming task of assuring pci specification compliance. the S5920?s design incorporates years of design experience and system knowledge achieved through the popular s5933 pci matchmaker device. the S5920 converts complex pci bus signals into an easy-to-use 8-, 16- or 32-bit user bus referred to as the add-on local bus. the S5920 add-on signal pins, shown in figure 2, provide the designer with a much simpler bus structure in which to interface i/o, memory or data acquisition applications and to port existent isa-based designs over to the pci bus. the bus can be operated either synchronously or asynchronously to the pci local bus with user definable clock speeds from 8 to 40 mhz. since the S5920 is a pci ?target? or ?slave? device only, its cost is significantly less than pci bus master solutions making it ideal for low cost applications. the S5920 is compliant with the pci local bus specification revision 2.2. it is capable of 132 mbytes/sec data transfer rates and supports both burst and single dword data transfers. the S5920 logic core is powered from a single 5 volt supply and utilizes advanced amcc technology to achieve low system power consumption at clock speeds to 33 mhz. the S5920 block diagram is shown in figure 1. the S5920?s superior feature set offers the designer multiple hardware and software design options for higher perfor- mance. up to four host bus memory or i/o space definable blocks, referred to as pass-thru regions, may be imple- mented providing multiple data channels. data transfers via a pass-thru data channel can be performed through a single buffered to the application or through burstable fifos. added read prefetch and programmable fifo wait state features allow the user to fine tune system performance. the pass-thru data channels also supports an ?active or passive? mode bus interface. passive mode requires the designer to transfer data by externally driving data onto the add-on bus. active mode minimizes design components by enabling internal logic to drive or acquire the add-on bus for reading or writing data independently. active mode also supports programmable wait state generation for slower add-on designs.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 2 S5920 32-bit pci bus target interface add-on bus timing/interrupts S5920 data access control pass-thru control/access serial bus config/bios opt. pci local bus S5920 control add-on data bus add-on bus control mail box access/control bpclk adclk sysrst# irq# addint# dq[31:0] select# adr[6:1] be[3:0]# rd# wr# ptatn# ptburst# ptnum[1:0] ptbe[3:0]# ptadr# ptwr ptrdy#/wait# dxfer# ptmode dqmode md[7:0] load# mdmode sda scl pclk inta# rst# ad[31:0] c/be[3:0]# frame# devsel# irdy# trdy# idsel# stop# lock# par perr# serr# flt# S5920 p c i l o c a l b u s user application serial bus operation/status registers mailboxes/status pass-thru address register pci pass- thru 32-byte fifo add-on pass- thru 2.1 pci local bus interface logic mux/demux data buffers serial read/write control pci configuration registers satellite receiver/ modem proprietary backplane graphics/ mpeg/ grabber isdn fddi atm isa design serial nvram configuration space expansion bios 32-byte fifo amcc add-on local bus interface logic mux/demux active r/w logic buffers serial read/write control the S5920 signal pins are shown in figure 2. the pci local bus signals are detailed on the left side; add-on local bus signal are detailed on the right side. all additional S5920 device control signals are shown on the lower right side. the S5920 provides two 32-bit mailbox registers for data transfers or user definable status/com- mand information transfer. each mailbox may be examined for an empty or full status, at the byte level, through a mailbox status register. mailbox transfers can be performed either by register style accesses (rd#/wr#, adr[6:2], select#, etc.) or hardware style accesses (md[7:0] and load#). the dedicated external mailbox data and strobe signal pins are provided for direct hard- ware read/writes with additional add-on to pci interrupt capabilities. a direct pci to add-on bus interrupt pin is also provided adding further design flexibility. the S5920 supports a two wire serial nvram bus. this allows the designer to customize the S5920 configuration by loading setup informa- tion during system power-up initialization from a single nvram and gain access to other devices on the serial bus. figure 2 figure 1
6290 sequence drive, san diego, california 92121-4358 800-755-2622 3 S5920 32-bit pci bus target interface S5920 scl sda 4.7k a0 a1 a2 4.7k serial nvram v cc v cc device id pci status class code base address register 0 base address register 2 base address register 4 reserved space expansion rom base address reserved space built-in self test header type subsystem id reserved space max. latency min. grant vendor id pci command revision id base address register 1 base address register 3 base address register 5 cacheline size latency timer subsystem vendor id interrupt line interrupt pin byte 3 byte 2 byte 0 byte 1 address 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch the S5920 register architecture all S5920 communications, control and configuration set up is performed through three groups of registers: pci configu- ration registers, pci operation registers and add-on operation registers. all of these registers are user configurable through their associated buses with boot loadable registers configured from the external nvram. the following provides a brief overview of each register group. the S5920 supports boot loading of configuration data, expansion bios and power-on self test code via the external nonvolatile serial memory device. the serial nvram may be programmed with user-defined configuration information which is loaded into the S5920 during power up initialization. programming or reading the nvram may be done any time from dedicated S5920 operation registers. the utilization of the expansion bios feature allows product identifica- tion banners or other user software code set-up requirements to be implemented during power up ini- talization. the serial nvram connections are shown in figure 3. figure 3 pci configuration registers all pci compliant devices are required to provide a group of pci configuration registers. these registers are polled by the host system bios during power-up initialization. they contain specific device and product information such as vendor id, device id, subsystem ven- dor id, memory requirements, etc. these registers are located in the S5920 and are either initialized with predefined default values or user customized defini- tions contained in the external nvram. table 1 shows the S5920 pci configura- tion registers. pci operation registers the second group of registers, shown in table 2, are the pci operation registers. this group of registers is accessible via the pci bus. these are the primary reg- isters through which the pci host con- figures the S5920 operation and communicates with the add-on bus. these registers encompass the pci bus mailboxes, pass-thru/fifo data chan- nel and status/control registers. table 1
6290 sequence drive, san diego, california 92121-4358 800-755-2622 4 S5920 32-bit pci bus target interface pci operation registers outgoing mailbox register (omb) incoming mailbox register (imb) mailbox empty/full status register (mbef) interrupt control/status register (intcsr) reset control register (rcr) pass-thru configuration register (ptcr) address offset 0ch 1ch 34h 38h 3ch 60h add-on bus operation registers add-on incoming mailbox register (aimb) add-on outgoing mailbox register (aomb) add-on pass-thru address register (apta) add-on pass-thru data register (aptd) add-on maibox empty/full status register (ambef) add-on interrupt control/status register (aint) add-on reset control register (arcr) add-on pass-thru configuration register (aptcr) address offset 0ch 1ch 28h 2ch 34h 38h 3ch 60h 8 8 8 8 p c i b u s 8 mailbox byte 0 mailbox byte 1 mailbox byte 2 mailbox byte 3 mailbox status register 8 8 8 32 add-on decode control 32 pci decode control 32 mailbox byte 0 mailbox byte 1 mailbox byte 2 mailbox byte 3 8 / 1 6 / 3 2 a d d - o n b u s 32 32 mailbox operation the mailbox registers are divided into two 4 byte sets. each set is dedicated to one bus for data transfer to the other bus. figure 4 shows a block diagram of the mailbox section of the S5920. the provision of mailbox registers provides data or user defined command/status transfer capability between two busses. an empty/full indication for each mailbox register, at the byte level, is determined by polling a status register accessible to both the pci and add-on busses. providing mail- box byte level full indications allows greater flexibility in 8, 16 or 32 bit designs; i.e., transferring a single byte on a 32- bit add-on bus without requiring the assembly or disassembly of 32 bit data. a mailbox byte level interrupt feature for pci or add-on busses is provided. bit locations configured within the S5920 operation registers can select which mailbox byte is to generate an interrupt when the mailbox is written to. interrupts can add-on bus operation registers the last register group consists of the add-on operation registers shown in table 3. this group of registers is accessible via the add-on bus. these are the primary registers through which the add-on application configures S5920 operation and communicates with the pci bus. these registers encompass the add-on bus mailboxes, pass-thru/fifo registers and status/control registers. table 2 table 3 figure 4
6290 sequence drive, san diego, california 92121-4358 800-755-2622 5 S5920 32-bit pci bus target interface p c i b u s pass-thru register endian conv. 32-byte fifo status/ctrl register add-on decode control 32 pci decode control 32 8 / 1 6 / 3 2 a d d - o n b u s 32 endian conv. 32-byte fifo pass-thru register 32 has been requested. user logic decodes these signals to determine if it must read or write data to the S5920 to satisfy the pci request. information decoded includes: pci read/write transaction request, the byte lanes involved, the specific pass- thru region accessed and the request is a burst or single cycle access. pass-thru operation supports single pci data cycles and pci data bursts. during pci burst operations, the S5920 is capa- ble of transferring data at the full pci bandwidth. should slower add-on logic be implemented, the S5920 will issue a pci bus retry until the requested transfer is completed. to increase data throughput, the pass-thru channel incorporates two 32 byte fifos. one fifo is dedicated to pci read data while the other is dedicated to pci write data. enabling the write fifo allows the S5920 to accept zero wait state bursts from the pci bus regardless of the add-on bus application design speed. enabling the read fifo allows data to be optionally prefetched from the add-on bus. this can greatly improve perfor- mance of slow add-on bus designs. pci read cycles can be performed with zero wait states since data has been prefetched into the fifo. either of the write/read fifos can be disabled or enabled to tune system performance. the add-on bus can be operated in two different modes: active or passive. the passive mode of operation mimics that of the s5933 add-on bus operation. the user design drives S5920 pins to read or write data. in active mode, the add-on bus is driven from an S5920 internal state machine. this reduces component count in cost sensitive designs. active mode also incorporates programmable wait states from 0 to 7. be generated to the pci or add-on buses. pci bus interrupts may also be generated from direct hardware interfacing due to a unique S5920 feature. the add-on mailbox is hardware accessible via a set of dedicated device pins. a single load pulse latches data into the mailbox generating an interrupt, if enabled. pass-thru operation pass-thru region accesses can execute pci bus cycles in real time or through an internal fifo. real time operation allows the pci bus to directly read or write to add-on bus resources. the S5920 allows the designer to declare up to four individ- ual pass-thru regions. each region may be defined as 8, 16 or 32 bits wide, mapped into memory or i/o system space and may be up to 512 mb in size. figure 5 shows a block diagram of the S5920 pass-thru architecture. host communications to the pass-thru data channel utilizes dedicated add-on bus pins to signal that a pci read or write figure 5
6290 sequence drive, san diego, california 92121-4358 800-755-2622 6 S5920 32-bit pci bus target interface S5920 p i n d e s c r i p t i o n s ad[31:0] t /s address/data. address and data are multiplexed on the same pci bus pins. a pci bus transac- tion consists of an address phase followed by one or more data phases. an address phase occurs on the pclk cycle in which frame# is asserted. a data phase occurs on the pclk cycles in which irdy# and trdy# are both asserted. c/be[3:0]# in command/byte enable . bus commands and byte enables are multiplexed on the same pins. these pins define the current bus command during an address phase. during a data phase, these pins are used as byte enables, with c/be[0]# enabling byte 0 (lsb) and c/be[3]# enabling byte 3 (msb). c/be# [3 2 1 0] description 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 memory read 0 1 1 1 memory write 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 0 1 dual address cycle 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate par t/s parity . parity is always driven as even from all ad[31:0] and c/be[3:0]# signals. the parity is valid during the clock following the address phase and is driven by the bus master. during a data phase for write transactions, the bus master sources this signal on the clock following irdy# active; during a data phase for read transactions, this signal is driven by the target and is valid on the clock following trdy# active. the par signal has the same timing as ad[31:0], delayed by one clock. pclk in pci clock . the rising edge of this signal is the reference upon which all other signals are based except for rst# and inta#. the maximum pclk frequency for the S5920 is 33 mhz and the minimum is dc (0 hz). rst# in reset is used to bring the S5920 to a known state: - all pci bus output signals tri-stated. - all open drain signals (i.e. serr#) floated. - all registers set to their factory defaults. - pass-thru is returned to an idle state. - all fifos emptied. frame# in frame . this signal is driven by the current bus master to indicate the beginning and duration of a bus transaction. when frame# is first asserted, it indicates a bus transaction is beginning with a valid addresses and bus command present on ad[31:0] and c/be[3:0]. data transfers continue while frame# is asserted. frame# de-assertion indicates the transaction is in a final data phase or has completed.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 7 S5920 32-bit pci bus target interface irdy# in initiator ready . this signal is always driven by the bus master to indicate it's ability to com- plete the current data phase. during write transactions, it indicates ad[31:0] contains valid data. trdy# s/t/s target ready . this signal is driven by the selected target to indicate the target is able to com- plete the current data phase. during read transactions, it indicates ad[31:0] contains valid data. wait states occur until both trdy# and irdy# are asserted together. stop# s/t/s stop . the stop signal is driven by a selected target and conveys a request to the bus master to stop the current transaction. lock# in lock . the lock signal provides for the exclusive use of a resource. the S5920 may be locked by one master at a time. idsel in initialization device select . this pin is used as a chip select during configuration read or write transactions. devsel# s/t/s device select . this signal is driven by a target decoding and recognizing its bus address. this signal informs a bus master whether an agent has decoded a current bus cycle. inta# o/d interrupt a . this signal is defined as optional and level sensitive. driving it low will interrupt to the host. the inta# interrupt is to be used for any single function device requiring an inter- rupt capability. perr# s/t/s parity error . only for reporting data parity errors for all bus transactions except for special cycles. it is driven by the agent receiving data two clock cycles after the parity was detected as an error. this signal is driven inactive (high) for one clock cycle prior to returning to the tri- state condition. serr# o/d system error . used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. special cycle commands are not supported by the S5920. scl o/d out serial clock . this clock provides timing for all transactions on the two-wire serial bus. the S5920 drives this signal when performing as a serial bus master. scl operates at the maximum allowable clock speed and enters the high z state when flt# is asserted or the serial bus is inactive. sda o/d serial data/address . this bi-directional signal carries serial address and data information between nvrams and the S5920. this pin enters high z state when flt# is asserted or the serial bus is inactive. mdmode in mailbox data mode . the md[7:0] signal pins are always inputs when this signal is high. the md[7:0] signal pins are defined as inputs and outputs under load# control when mdmode is low. this pin is provided for software compatibility with the s5933. new designs should permanently connect this signal low. this signal is connected to an internal pull-up. load# in md[7:0] is defined as an input bus when this signal is low. the next rising edge of the adclk will latch md[7:0] data into byte three of the add-on outgoing mailbox. when load# is high and mdmode is low, md[7:0] are defined as outputs displaying byte three of the pci outgoing mailbox. this signal is connected to an internal pull-up. md[7:0] t/s mail box data bus . the mail box data registers can be directly accessed using the load# and mdmode signals. when configured as an input, data byte three of the pci incoming mailbox is directly written to from these pins. when configured as an output, data byte three of the pci outgoing mailbox is output to these pins. all md[7:0] signals have an internal pull-up.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 8 S5920 32-bit pci bus target interface ptmode in pass-thru mode . configures the pass-thru data channel operation. high configures the S5920 in passive mode allowing other devices to read/write data bus data. low configures the S5920 in active mode. this mode allows the S5920 to actively drive signals and data onto the data bus. this signal is connected to an internal pull-up. ptatn# out pass-thru attention . signals a decoded pci to pass-thru region bus cycle. ptatn# is gener- ated to signal add-on logic pass-thru data must be read from or written to the S5920. ptburst# out pass-thru burst . informs the add-on bus the current pass-thru region decoded pci bus cycle is a burst access. ptrdy#/wait# in pass-thru ready/pass-thru wait . during passive mode, the signal is referred to as ptrdy# and is asserted low to indicate add-on logic has read/written data in response to a ptatn# signal. during active mode operation, the signal is referred to as wait# and can be driven high to insert wait states or hold the S5920 from clocking data onto the data bus. ptrdy# or wait# is synchronous to adclk. this signal is synchronous to adclk. ptnum[1:0] out pass-thru number . identifies which of the four pass-thru regions the ptatn# read/write is requesting. only valid for the duration of ptatn# active. 00 = base address register 1, 01 = base address register 2, 10 = base address register 3, 11 = base address register 4. ptbe[3:0]# out pass-thru byte enables . during a pci to pass-thru read, indicates which bytes of a dword is to be written into. during a pci to pass-thru write, indicates which bytes of a dword are valid to read. ptbe[3:0]# are only valid while ptatn# is asserted. ptadr# t/s pass-thru address . is an input when in passive mode. when asserted, the 32-bit pass-thru address register contents are driven onto the dq[31:0] bus. all other add-on control signals must be inactive during the assertion of ptadr# in passive mode. in active mode, becomes an output and indicates a pass-thru address is on the dq bus. the dqmode signal does not affect dq bus width while the pass-thru address is driven. ptwr out pass-thru write . this signal indicates the current pci to pass-thru bus transaction is a read or write cycle. valid only when ptatn# is active. dxfer# out data transfer . active transfer complete. when in active mode, this output is asserted at the end of every 8, 16 or 32 bits data transfer cycle. this signal is not used in passive mode. dq[31:0] t/s address/data bus . the 32 bit add-on data bus. the dqmode signal configures the bus width for either 32 or 16 bits. all dq[31:0] signals have an internal pull-up. adr[6:2} in address [6:2]. these inputs select which S5920 register is to be read from or written to. to be used in conjunction with select#, be[3:0]# and wr# or rd#. the following table shows the register addresses. adr [6 5 4 3 2] description 0 0 0 1 1 add-on incoming mailbox register 0 0 1 1 1 add-on outgoing mailbox register 0 1 0 1 0 add-on pass-thru address register 0 1 0 1 1 add-on pass-thru data register 0 1 1 0 1 add-on mailbox status register 0 1 1 1 0 add-on interrupt control register 0 1 1 1 1 add-on reset control register 1 0 0 0 0 pass-thru/fifo configuration register
6290 sequence drive, san diego, california 92121-4358 800-755-2622 9 S5920 32-bit pci bus target interface be[2:0]# in byte enable [2:0] . provides individual read/write byte enabling during register read or write transactions. be2# enables activity over dq[23:16], be1# enables dq[15:8], and be0# enables dq[7:0]. during read transactions, enables the output driver for each byte lane; for write transactions, serves as an input enable to perform the write to each byte lane. be3#/adr1 in byte enable 3/address 1 . 32-bit bus width/16-bit bus width. be3#, enables dq[31:24] input drivers for writing data to registers identified by adr[6:2] and enables dq[31:24] output driv- ers to read registers identified by adr[6:2]. to be used in conjunction with select# and rd# or wr#. adr1, selects the upper or lower word of a dword when a 16 bit wide bus is selected. 1 = lower, 0 = upper. select# in select . enables internal S5920 logic to decode wr#, rd# and adr[6:2] when reading or writing to any add-on register. wr# in write enable . asserting this signal writes dq bus data byte(s) selected by be[3:0]# into the S5920 register defined by select# and adr[6:2]. rd# in read enable . asserting this signal drives data byte(s) selected by be[3:0]# from the S5920 register defined by select# and adr[6:2] onto the dq bus. dqmode in dq mode . defines the dq bus width when accessing data using wr#, rd#, select# and adr[6:2]#. low = 32-bit wide dq bus. high = 16-bit wide dq bus. when high, the signal be3# is re-assigned to the adr1 signal and only dq[15:0] is active. sysrst# out system reset . an active-low buffered pci bus rst# output signal. the signal is asynchronous and can be asserted through software from the pci host interface. bpclk out buffered pci clock . this output is a buffered form of the pci bus clock and has all of the behavioral characteristics of the pci clock (i.e., dc-to-33 mhz capability). adclk in add-on clock . all internal S5920 add-on bus logic is synchronous to this clock. the clock is asynchronous to the pci bus logic unless connected to the bpclk signal. irq# out interrupt request . this output signals add-on logic a significant event has occurred as a result of activity within the S5920. addint# in add-on interrupt . when enabled and asserted, this input will cause a pci bus interrupt by driv- ing inta# low. the input is level sensitive and can be driven by multiple sources. this signal is connected to an internal pull-up. flt# in float . floats all S5920 output signals when asserted. this signal is connected to an internal pull-up.
6290 sequence drive, san diego, california 92121-4358 800-755-2622 10 S5920 32-bit pci bus target interface adclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# 0 1 2 3 4 adr[6:2] be[3:0]# wr# dq[31:0] ptadr# ptrdy# 5 6 7 8 9 10 11 12 13 addr d1 d2 data 1 data 2 d3 d4 data 3 data 4 0h 0h fh 2ch adclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0] select# 0 1 2 3 4 adr[6:2] be[3:0]# rd# dq[31:0] ptadr# addr ptrdy# 5 6 7 8 9 10 11 12 13 d1 d2 d3 data1 data2 data3 2ch 0h 0h 0h 3h d4 fh 0h data4 t i m i n g d i a g r a m s pci to add-on passive burst write pci to add-on passive burst read
6290 sequence drive, san diego, california 92121-4358 800-755-2622 11 S5920 32-bit pci bus target interface adclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0 1 2 3 4 dxfr# dq[31:0] ptadr# ptwait# 5 6 7 8 9 10 11 12 13 data3 1h data1 data1 data2 data4 fh data2 data3 data4 ptaddr adclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0 1 2 3 4 dxfr# dq[31:0] ptadr# ptwait# 5 6 7 8 9 10 11 12 13 ptaddr fh 14 data2 data1 data1 data2 data3 1h data3 active mode pci write showing a one wait state programmed delay active mode pci write showing a one wait state programmed delay
6290 sequence drive, san diego, california 92121-4358 800-755-2622 12 S5920 32-bit pci bus target interface symbol parameter min test conditions nom max units v cc pci supply voltage (core) high level input voltage low level input voltage high level output voltage low level output voltage pclk cycle time pclk high/low time rise/fall time ambient temperature power dissipation 4.75 2.0 -0.5 2.4 - 10 0 0 - - - - - tbd 5.25 v cc 0.8 - 0.4 2.5 70 tbd volts volts volts volts volts ns ns ns o c watts to pci spec 2.2 i oh = tbd v ih v il v oh v ol t c t w t r t a p dd i ol = tbd 25 supply current (static) supply current (dynamic) - 49 197 ma ma i cc i cc @33 mhz - input pin capacitance clk pin capacitance idsel pin capacitance - 5 - - - - 10 12 8 pf pf pf c in c clk c idsel a b s o l u t e m a x i m u m r a t i n g s supply voltage range (v cc core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to 7.0 v input pin voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to vcc + 0.5 v storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125 c operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70 c virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c soldering lead temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c 10 seconds ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to this device. these are stress ratings only. r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s
6290 sequence drive, san diego, california 92121-4358 800-755-2622 13 S5920 32-bit pci bus target interface stop# perr# clk rst # c/be0# irdy# devsel# flt# idsel# ad0 par dqmode frame# trdy# serr# ptburst# ptatn# inta# ptadr# ptwr ptrdy#/wait# rsvd5 rsvd2 rsvd4 s c l sda master0 holda hold ptbe2# ptbe0# ptnum1 ptnum0 be3#/adr1 be2# be1# bpclk be0# sysrst# adr6 adr5 adr4 pci bus data bus md4 ptmode md3 md2 md1 md0 mail box bus nvram bus ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c/be1# c/be2# c/be3# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 adclk irq# addint# dxfr# adr2 adr3 select# wr# rd# ptbe1# ptbe3# master1 md5 56 55 54 52 48 47 46 44 42 40 39 38 36 35 34 32 14 12 8 7 6 4 3 2 158 156 155 154 152 148 147 146 43 28 15 159 27 142 139 16 20 18 19 160 22 59 138 24 26 136 113 149 58 114 112 107 108 115 127 128 57 61 69 73 104 81 89 74 72 122 123 116 118 119 120 c19 d18 a20 b20 126 144 68 67 66 64 132 87 63 62 60 75 117 105 93 85 77 65 53 45 37 25 13 5 140 134 124 102 95 94 92 88 86 84 83 82 80 79 78 76 157 145 133 125 100 99 98 96 S5920 pin connections lock# 23 rsvd3 135 rsvd1 29 load# md6 mdmode 97 109 143 load# 101 pass-thru data controls register access controls bus controls S5920 controls gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 1 9 10 17 21 30 41 49 50 70 90 106 110 121 130 137 141 150 153 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 11 31 33 51 71 91 103 111 129 131 151 power & ground add-on user bus
6290 sequence drive, san diego, california 92121-4358 800-755-2622 14 S5920 32-bit pci bus target interface detail a j radius l h k g b a a c a2 a1 a see detail a 0.10 c -c- seating plane d d1 e e1 pin 1 indicator b e symbol min nom a a1 a2 d d1 e e1 0.80 l e b c - 0.25 3.17 31.90 bsc 0.65 0.22 0.11 max 4.07 1.03 0.38 0.23 a b g g h j k 3.9 2h 5 0 0 0.13 0.13 0.40 16 7 0.30 28.00 bsc 31.90 bsc 28.00 bsc 0.65 bsc 1.95 bsc - - - - - - - - - - - - - - - - - - p a c k a g e i n f o r m a t i o n 160 pqfp
6290 sequence drive, san diego, california 92121-4358 800-755-2622 15 S5920 32-bit pci bus target interface the material in this document supersedes all previous documentation issued for any of the products included herein. amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its custom- ers to obtain the latest version of relevant information to verify, before plac- ing orders, that the information being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patents rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. copyright ? 1998 applied micro circuits corporation
6290 sequence drive, san diego, california 92121-4358 800-755-2622 16 S5920 32-bit pci bus target interface a p p l i e d m i c r o c i r c u i t s c o r p o r a t i o n s a l e s a n d r e p r e s e n t a t i v e s o f f i c e s united states regional sales managers southwest mike vogel (949) 366-4105 northwest sam laymoun (408) 289-1190 mid-us george amundson (972) 423-7989 northeast dave crary (781) 270-0674 southeast joey carabetta (919) 558-2003 factory application engineers northwest issa shokeh (408) 289-1194 mid-us wes stalcup (972) 422-7174 northeast mike sluyski (781) 270-0674 southeast john king (972) 509-0782 representatives centaur north san jose (408) 894-0182 century tech. sales loveland, oh (513) 677-5088 westlake, oh (216) 808-9171 columbus, oh (614) 433-7500 wexford, pa (412) 934-2326 indianapolis, pa (317) 876-0101 lexington, ky (606) 276-3164 novi, mi (248) 344-2550 cetan timonium, md (410) 453-0969 comprep associates westwood, ma (781) 329-3454 customer 1st bloomington, mn (612) 851-7909 overland, ks (913) 895-9593 delta tech sales hatboro, pa (215) 957-0600 dynamic tech old saybrook, ct (860) 388-0130 era, inc. cammack, ny (516) 543-0510 first source sandy, ut (801) 561-1999 glenn white associates huntsville, al (205) 882-6751 duluth, ga (770) 418-1500 raleigh, nc (919) 848-1931 huntersville, nc (704) 875-3777 harper & two san diego, ca (619) 549-5366 signal hill, ca (562) 424-3030 l-squared ltd. beaverton, or (503) 646-7747 kirkland, wa (206) 525-8555 logic 1 sales, inc. richardson, tx (972) 234-0765 austin, tx (512) 345-2952 houston, tx (281) 444-7594 luscombe eng. co. longmont, co (303) 772-3342 parker, co (303) 814-9725 mega technologies, inc. melbourne, fl (407) 752-6767 tampa, fl (813) 797-8222 wilton manors, fl (954) 563-1882 phase ii marketing, inc. rolling meadows, il (847) 577-9401 brookfield, wi (414) 797-9986 quality components manlius, ny (315) 682-8885 quatra associates phoenix, az (602) 753-5544 albuquerque, nm (505) 296-6781 insight electronics u.s. distributor (800) 677-7716 europe/israel general manager richard matysiak 49-89-92404-217 factory application engineer giovanni castellano 39-2-4986244 representatives denmark dan-contact 45-39-683633 france a2m 33-1-46237900 sildesign 33-1-644-63576 germany tekelec airtronic munich 49-89-51640 hamburg 49-453-429-1150 israel eldis technologies ltd. 972-9-9562666 italy acsis s.r.l. 39-248022522 esco italiana spa 39-2-2409241 netherlands tekelec airtronic b.v. 31-79-346-1430 norway bit elektronikk a.s. 47-66-77-65-00 u.k. amega electronics 44-1256-305-330 sweden dipcom 46-8-752-2480 switzerland ixlogic ag 41-1-434 78 10 pacific asia general manager sunny chow (619) 535-6526 factory application engineer michael sedayao (619) 535-6873 representatives korea buksung ind. co. ltd. 82-2-866-1360 singapore gates engineering pte ltd. 65-299-9937 taiwan hsien johnson trading co. 866-2-2999-8281 promate elec co. ltd. 886-2-6590303 japan teksel co., ltd. 81-35467-9104 hong kong twin-star trading co. 852-2341-4282 canada regional sales manager dave crary (781) 270-0674 factory application engineer mike sluyski (781) 270-0674 representatives electronic sales prof. nepean, ont. (613) 828-6881 toronto, ont. (905) 856-8448 st. laurent, que. (514) 344-0420 australia insight electronics pty ltd. 61-3-9761-3455 new zealand 64-9-636-5984 india interex 91-80-640-663

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